1. Field of the Invention
This invention relates generally to fabrication of integrated circuits, and more particularly to providing an improved gate conductor for enhanced transistor operation by introducing a diffusion barrier into the bottom layer of a stacked gate conductor.
2. Description of the Related Art
MOSFETs (metal-oxide-semiconductor-field-effect transistors) are the basic building blocks of modern integrated circuits. The conventional fabrication of MOSFET devices is well known. Typically, MOSFETs are manufactured by depositing an undoped polycrystalline silicon ("polysilicon") material over a relatively thin gate oxide arranged above a semiconductor substrate. The polysilicon material and the gate oxide are patterned to form a gate conductor arranged between a source region and a drain region. The gate conductor and source/drain regions are then implanted with an impurity dopant. If the dopant species employed for forming the source/drain regions is n-type, then the resulting MOSFET is an NMOSFET (n-channel) transistor device. Conversely, if the source/drain dopant species is p-type, then the resulting MOSFET is a PMOSFET (p-channel) transistor device. Integrated circuits utilize either n-channel devices exclusively, p-channel devices exclusively, or a combination of both on a single monolithic substrate.
The number of transistors per unit area in modern semiconductor devices continues to increase. Commensurately, device geometries continue to decrease. Moving to smaller device dimensions exacerbates some common problems encountered in transistor fabrication. One such problem shared by all MOS transistor devices is unwanted impurity diffusion from the source/drain regions. As is well known in the art, impurities are used to augment carrier transport and electrical performance in transistors. Controlled diffusion of impurities can be an important step in a process flow. Thus, thermal diffusion is often required subsequent to implanting source/drain regions in order to activate dopants and repair lattice damage. However, unwanted migration or diffusion can occur during processing or transistor operation that degrades performance. Problems associated with diffusion, both in the lateral and vertical dimensions, become more acute as device geometries shrink. One important lateral dimension is the channel length of transistor, which is defined by the spacing between the source and drain regions. One problem associated with small channel lengths is short channel effects, which impact device operation by reducing threshold voltages and increasing sub-threshold currents. Generally, short channel effects are exacerbated by lateral diffusion caused by thermal steps in a process flow.
The drawbacks associated with diffusion from source/drain regions are more pronounced in PMOS devices. This is attributable to the differences in the characteristics of the typical impurities used in NMOS and PMOS devices. Arsenic is generally used to form source/drain regions in NMOS transistors. Heavy As atoms diffuse relatively slowly in silicon, thereby allowing source/drain regions doped with As to remain relatively shallow during high temperature anneal steps that must be performed subsequent to source/drain implantation. Additionally, the implantation of heavy arsenic atoms tends to amorphize the silicon in the source/drain regions. Amorphization decreases diffusion by inhibiting channeling. Channeling can occur when ions are forwarded into single crystal lattices, such as silicon, because there are some crystal directions, so called "channels," along which the ions will not encounter any lattice nuclei. Implanted ions traveling along channels are stopped principally by electronic stopping. Consequently, the ions can penetrate the lattice to a much greater depth than in amorphous targets. In contrast, boron, which is a light atomic species, is generally used to dope PMOS source/drain regions. Lighter boron atoms diffuse relatively fast in silicon and do not amorphize silicon upon implantation. The channeling problem can be partially solved by using boron difluoride (BF.sub.2) as the implant species. However, use of BF.sub.2 does not reduce the problem of boron diffusion. Inhibition of boron diffusion is usually accomplished with a diffusion barrier. Common barrier species include nitrogen, argon, and germanium.
Vertical diffusion in gate conductors presents another problem affecting the performance of modern MOS devices. As mentioned above, a gate conductor is typically formed by patterning a layer of polysilicon deposited over a thin gate dielectric. Impurities are often introduced into a gate conductor by implantation to increase the electrical properties of the polysilicon. Boron is a typical candidate. A boron implant into the gate conductor may be performed as a separate step. Alternatively, in PMOS devices boron may be introduced into the gate conductor during the formation of source/drain regions where the gate conductor is used to align the source/drain implants. A p.sup.+ dopant of boron may penetrate, diffuse, or migrate through the thin gate dielectric from the gate conductor to the underlying channel region. Proper operation of a PMOS device requires maintaining a closely controlled n-dopant level in the channel region. Boron introduction into the channel region of a PMOS device will cause a change in the n-dopant concentration. Even a slight change in the channel concentration will adversely shift the threshold voltage, VT, of the device. Therefore, in designing a PMOS device, not only must the lateral and vertical diffusions out of the source/drain regions be minimized and controlled as described above, but the outdiffusion of boron from the polysilicon gate conductor through the thin gate dielectric must also be minimized and controlled.
One approach to inhibiting vertical diffusion of boron from a gate conductor is to mask the gate conductor prior to doping the source and drain regions. For example, titanium silicide deposited on the upper surface of the gate conductor will substantially block boron (or BF.sub.2) from being implanted into the gate: Absence of boron (or BF.sub.2) in the gate conductor will therefore ensure that it will not subsequently enter the channel via the gate. However, titanium silicide selectively placed across only the gate conductor region before source/drain implantation generally requires a separate masking step and associated photolithography. Moreover, the masking step must eventually be repeated in order to provide a high conductivity over the source/drain contacts after the source/drain regions are implanted. Requiring two photolithography steps and associated masks can prove problematic and should in most cases be avoided if only one step is needed. Alternatively, titanium silicide can be placed across the entire active area (gate and source/drain regions) prior to a high-energy implantation through the silicide. Blanket deposition of titanium silicide in the active regions follows normal processing flow without requiring additional masks or steps. However, blanket deposition and subsequent high-energy implantation cannot ensure BF.sub.2 is prevented from entering the gate while permitting accurate (e.g., shallow) implantation into the source/drain.
Another approach to inhibiting vertical diffusion of boron from a gate conductor is to provide a diffusion barrier within the gate. Germanium atoms have been used to form such a barrier. A diffusion barrier may be formed by a blanket implantation of germanium ions to a depth below the subsequently implanted boron ions. Placement of the germanium barrier in the gate conductor intermediate the gate oxide and the boron implant substantially prevents or retards penetration or migration of the boron ions from the gate conductor into the underlying channel region. However, optimal functionality of the diffusion barrier hinges on carefully locating the germanium ions at the proper depth within the gate. Moreover, the germanium ion distribution must be relatively dense in order (i.e., the germanium ions must be arranged fairly close to one another) to effectively inhibit diffusion and channeling of the boron ions. Controlling the density and depth of the implant becomes more difficult as the desired depth of the diffusion barrier increases. It would be advantageous to be able to more accurately control the location and density of the diffusion barrier within the gate conductor.